Manufacturing of integrated circuits on semiconductor wafers may involve numerous stages of fabrication and processing, and may thus require several processes for detecting fabrication errors. When significant fabrication errors are found on a wafer or a batch of wafers, such that the wafers are defective and unusable, fabrication tools may need to be shut down and adjusted or fixed to prevent further fabrication of wafers with such significant errors. However, many techniques for detecting fabrication errors have a high “false alarm” rate, causing fabrication tools to be needlessly shut down and wasting valuable manufacturing and engineering time, as well as greatly reducing productivity and wafer yield.